Subjecting a transistor within an integrated circuit to over-voltage conditions, e.g., placing a voltage across the source-to-drain terminals of a transistor that exceeds the transistor's maximum source-to-drain rating, places an over-voltage stress on the transistor. Transistors in circuits designed to amplify, or shift upwards, the voltage level of an incoming signal are particularly susceptible to design oversights and/or other conditions that result in over-voltage stress being applied to one or more transistors in the circuit. Such circuits are often used to support physical interfaces between circuits that operate using different e.g., higher, operating voltages. Such level-shifting circuits may be more likely to suffer from over-voltage conditions as a result of managing voltage levels that may exceed one or more maximum voltage ratings of individual transistors in the circuit. For example, level shifting circuits that support physical interfaces between devices may be vulnerable to over-voltage stress when physical devices are either connected or disconnected.
A single incident of over-voltage stress may not result in failure of the circuit. However, it is desirable to avoid over-voltage stress because regular incidents of over-voltage stress may eventually result in peimanent changes in the operational characteristics of a transistor, which may distort the operation of the circuit and/or result in failure of the circuit at a functional level.